The present invention relates to semiconductor devices comprising transistors with metal gate electrodes and improved gate dielectric layers. The present invention is particularly applicable in fabricaturing high speed semiconductor devices having submicron design features.
The integration of hundreds of millions of circuit elements, such as transistors, on a single integrated circuit necessitates further dramatic scaling down or micro-miniaturization of the physical dimensions of circuit elements, including interconnection structures. Micro-miniaturization has engendered a dramatic increase in transistor engineering complexity, such as the inclusion of graded well-doping, epitaxial wafers, halo implants, tip implants, lightly doped drain structures, multiple implants for source/drain regions, silicidation of gates and source/drains, and multiple sidewall spacers, for example.
The drive for high performance requires high speed operation of microelectronic components requiring high drive currents in addition to low leakage, i.e., low off-state current, to reduce power consumption. Typically, the structural and doping parameters tending to provide a desired increase in drive current adversely impact leakage current.
Recently, metal gate electrodes have evolved for improving the drive current by reducing polysilicon depletion, and reducing processing temperatures subsequent to metal gate formation. In order to implement replacement metal gate process flow, a dummy gate, such as polysilicon, is removed by dry/wet etching, followed by metal deposition.
Polysilicon dry etching is conventionally performed using a plasma. Metal deposition is conventionally performed using physical vapor deposition or sputtering, which also requires a plasma. However, the use of a plasma causes radiation damage to the gate oxide thereby adversely impacting transistor performance.
Accordingly, a need exists for methodology enabling the fabrication of micro-miniaturized semiconductor devices comprising transistors with metal gate electrodes having improved a gate dielectric quality.
An advantage of the present invention is a semiconductor device having a transistor with a metal gate electrode and a gate oxide with improved quality.
Another advantage of the present invention is a method of manufacturing a semiconductor device comprising a transistor with a metal gate electrode and a gate oxide of improved quality.
Additional advantages and other features of the present invention will be set forth in the description which follows and, in part, will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, the method comprising: forming a removable gate over a substrate with a gate dielectric layer therebetween; forming a dielectric layer over the substrate and exposing an upper surface of the removable gate; removing the removable gate leaving an opening in the dielectric layer exposing an upper surface of the gate dielectric layer, wherein the gate dielectric layer is damaged when removing the removable gate; depositing a conductive layer filling the opening and forming an overburden on the dielectric layer; and conducting chemical mechanical polishing (CMP); the method further comprising treating the gate dielectric layer to remedy the damage to the gate dielectric layer.
Embodiments of the present invention include forming a removable polysilicon gate over a gate oxide layer and treating the gate oxide layer at an elevated temperature. Embodiments of the present invention include annealing the gate oxide layer by vacuum annealing after chemical mechanical polishing. Embodiments of the present invention also include annealing after removing the removable gate and wet cleaning before depositing the conductive layer. Annealing before depositing the conductive layer may be conducted in oxygen and argon, ozone, or a forming gas, or by heat soaking in an atmosphere containing silicon, such as heat soaking in silane or disilane. Embodiments of the present invention also comprise forming a composite metal gate electrode comprising a tantalum silicon nitride liner and tantalum nitride filling the opening.
Another advantage of the present invention is a semiconductor device comprising: a substrate; a gate oxide layer on the substrate; a layer of silicon on the gate oxide layer; and a metal gate electrode on the layer of silicon.
A further aspect of the present invention is a semiconductor device having complimentary metal oxide (CMOS) devices including an NMOS transistor with a metal gate electrode and a PMOS transistor with a doped polysilicon gate electrode.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein embodiments of the present invention are described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modification in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.